Gestion des unités de mémorisation pour la synthèse d'architecture

Content Provider	Semantic Scholar
Author	Corre, Gwenolé
Copyright Year	2005
Abstract	Systems handle more and more complex applications. Memory becomes a bottleneck since the quantity of information increases. In this context, it is crucial to efficiently manage memory all along the design flow especially during the high level synthesis that offers good optimization opportunities. We propose a methodology to integrate the memory management unit into HLS flow. Data distribution and memory architecture is defined as set of constraints in our high-level synthesis design flow. We realize high-level synthesis under memory constraints to obtain a memory architecture and its associated address generators. We extend our methodology; it leads to a generic memory architecture to store specific data of DSP applications. We also introduced memory access management based on the kanban system that improves the anticipation of memory accesses. Our methodologies are integrated into our high level design flow and our tool GAUT. The proposed methodology could be extended to others domains
File Format	PDF HTM / HTML
Alternate Webpage(s)	https://tel.archives-ouvertes.fr/tel-00077288/document
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article