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A New Delay-Line Sharing Based CMOS Digital PWM Circuit
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hung, Yu-Cherng Tsai, Kuei-Ching |
| Copyright Year | 2013 |
| Abstract | This paper presents a new circuit design for digital pulse-width modulators (DPWM). This method improves the structure of hybrid DPWM to a more compact architecture by utilizing the separation of MSB (most significant bit) and LSB (least significant bit) groups. In addition, a delay-line function block is shared with MSB and LSB groups to reduce power consumption. HSPICE post-layout simulation shows that this new DPWM circuit operates successfully at 200 MHz clock frequency and has 1.55-mW power consumption. An experimental chip had been fabricated by using a standard 0.18 micron CMOS process. The layout area of the chip including I/O pads is 461 m×370 m. The new DPWM design carries the advantages of smaller chip area and low power consumption especially for the high resolution required. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.globalcis.org/ijact/ppl/IJACT1391PPL.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
