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Design and Analysis of Two-Stage Operational Transconductance Amplifier with Compensation Capacitor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kumari, Namika |
| Copyright Year | 2011 |
| Abstract | Visiting Faculty, ECE Dep., DCRUST Murthal For designing of high-performance analog circuits is still a hard task towards reduced supply and increased unity bandwidth. OTA is the basic element with highest power dissipation in many applications. In a handheld device, low power consumption is very essential so it is a challenge to design a low-power OTA with higher gain, low power dissipation and high CMRR. There is a compromise between again, speed, power and unity gain bandwidth because all these parameters depend on each other. A novel design procedure for CMOS two-stage operational transconductance amplifier is presented in this paper. A compensation compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency, and the Power dissipation. In this design supply voltage is 1.8v and simulated by using CADENCE VIRTUOSO tool at 180nm technology. The open loop gain of this OTA is about 70 dB, GBW is 500 MHz, CMRR is 117 dB and Power Dissipation is 174.25. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.everant.org/images/etjissue/v2-i3/1.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Analog Analogue electronics CMOS CPU power dissipation Capacitor Device Component Decibel Electrical engineering Frequency compensation Low-power broadcasting Megahertz Mobile device Operational transconductance amplifier Overhead (computing) ochratoxin A |
| Content Type | Text |
| Resource Type | Article |
