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Design techniques for high-speed low-power wireline receivers
| Content Provider | Semantic Scholar |
|---|---|
| Author | Yazd, Arash Zargaran |
| Copyright Year | 2013 |
| Abstract | High-speed data transmission through wireline links, either copper or optical based, has become the backbone for modern communication infrastructure. Since at multi-Gb/s data rates the transmitted signal is attenuated and distorted by the channel, sophisticated analog front-end and/or digital signal processing are required at the receiver (RX) to recover data and clock from the received signal. In this thesis, both analogand digital-based receivers are investigated, and power-reduction techniques are exploited at both systemand circuit-levels. A speculative successive-approximation register (speculative/SAR) digitization algorithm is proposed for use at the receiver front-end of digital receivers that combines equalization and data recovery with the digitization step at the front-end analog-to-digital converter (ADC). Furthermore, an architecture for quadrature clock generation is proposed which is of use in both analog and digital receivers. Then, an analog clock and data recovery (CDR) architecture suitable for high data rates (e.g., beyond 10 Gb/s) is proposed that utilizes a wideband data phase generation technique to facilitate mixer-based phase detection. The CDR architecture is implemented and experimentally validated for a 12.5 Gb/s system. Finally, a mixed-mode hardware-efficient CDR architecture is proposed that exploits both analog ii |
| File Format | PDF HTM / HTML |
| DOI | 10.14288/1.0072002 |
| Alternate Webpage(s) | https://open.library.ubc.ca/media/download/pdf/24/1.0072002/1 |
| Alternate Webpage(s) | https://doi.org/10.14288/1.0072002 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
