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A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lee, Hae-Seung |
| Copyright Year | 1996 |
| Abstract | This 1.2 /spl mu/m, 33 mW analog-to-digital converter (ADC) demonstrates a family of power reduction techniques including a commutated feedback capacitor switching (CFCS), sharing of the second stage of an op amp between adjacent stages of a pipeline, reusing the first stage of an op amp as the comparator pre-amp, and exploiting parasitic capacitance as common-mode feedback capacitors. |
| Starting Page | 314 |
| Ending Page | 315 |
| Page Count | 2 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/4.545805 |
| Alternate Webpage(s) | http://www-mtl.mit.edu/researchgroups/hslee/1854yu.pdf |
| Alternate Webpage(s) | http://www-mtl.mit.edu/wpmu/hslee/files/2005/02/1854yu.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/4.545805 |
| Journal | 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |