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Approximate-SAD Circuit for Power-efficient H.264 Video Encoding under Maintaining Output Quality and Compression Efficiency
| Content Provider | Semantic Scholar |
|---|---|
| Author | Le, Dinh Trang Dang Nguyen, Thi My Kieu Chang, Ik Joon Kim, Jinsang |
| Copyright Year | 2016 |
| Abstract | We develop a novel SAD circuit for power-efficient H.264 encoding, namely a-SAD. Here, some highest-order MSB’s are approximated to single MSB. Our theoretical estimations show that our proposed design simultaneously improves performance and power of SAD circuit, achieving good power efficiency. We decide that the optimal number of approximated MSB’s is four under 8-bit YUV-420 format, the largest number not to affect video quality and compression-rate in our video experiments. In logic simulations, our a-SAD circuit shows at least 9.3% smaller critical-path delay compared to existing SAD circuits. We compare power dissipation under iso-throughput scenario, where our a-SAD circuit obtains at least 11.6% power saving compared to other designs. We perform same simulations under two-and three-stage pipelined architecture. Here, our a-SAD circuit delivers significant performance (by 13%) and power (by 17% and 15.8% for two and three stages respectively) improvements. |
| Starting Page | 605 |
| Ending Page | 614 |
| Page Count | 10 |
| File Format | PDF HTM / HTML |
| DOI | 10.5573/JSTS.2016.16.5.605 |
| Volume Number | 16 |
| Alternate Webpage(s) | http://ocean.kisti.re.kr/downfile/crosscheck/ieek/JAKO201631642279718.pdf |
| Alternate Webpage(s) | https://doi.org/10.5573/JSTS.2016.16.5.605 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
