Loading...
Please wait, while we are loading the content...
Similar Documents
High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sudha, N. Naga Nayak, V. Narasimha Mudunuru, Suneel Babu, M. Nagesh Prasad, Baba Jyothi, M. Kalpana |
| Copyright Year | 2012 |
| Abstract | Comparators are basic building blocks for designing modern mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents a design for an on-chip high-speed dynamic latched comparator for high frequency signal digitization. The dynamic latched comparator consists of two cross coupled inverters comprising a total of 9 MOS transistors. The measurement and simulation results show that the dynamic latched comparator design has higher speed, low power dissipation and occupying less active area compared to double tail latched and pre-amplifier based clocked comparators. These comparators are used in PTL circuits, so we compared the application of a PTL circuits by using the above specified three comparator designs. The simulation results show that PTL circuit with dynamic latched comparator has occupied less active area and also having higher speed and lower power dissipation. The comparator schematics and corresponding layouts are implemented using spice and microwind tool. Keywords— Dynamic Latched Comparator, digitization |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijcsit.com/docs/Volume%203/Vol3Issue1/ijcsit2012030111.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
