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Applications to VLSI design and time-space tradeoffs
| Content Provider | Semantic Scholar |
|---|---|
| Author | Radhakrishnan, Jaikumar |
| Copyright Year | 2011 |
| Abstract | In today’s lecture, we will see two applications of communication complexity. First, we will prove a lower bound on the physical limitations of VLSI chips use communication complexity. Then, we we will shift our attention to Turing machines, both multi-tape and one-tape variants, and we will prove time-space tradeoffs for multi-tape TMs and time lower bounds for one-tape TMs using communication complexity. This lecture is based on Chapters 8 and 12 of Kushilevtiz and Nisan’s book on Communication Complexity [KN97]. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.tcs.tifr.res.in/~prahladh/teaching/2011-12/comm/lectures/l04.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |