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An FPGA-oriented Hardware Implementation of Richardson-Lucy Deconvolution Algorithm for Hyperspectral Images
| Content Provider | Semantic Scholar |
|---|---|
| Author | Avagian, Karine |
| Copyright Year | 2019 |
| Abstract | This work presents a method to reduce the spatial degradation in hyperspectral images caused during the image acquisition process. The degradation is modeled by a convolution with a Point Spread Function (PSF), which in this work, is assumed to be known. The three-dimensional hyperspectral images are modeled as a composition of two-dimensional independent images. Degradation is reduced by applying an accelerated Richardson-Lucy (RL) deconvolution algorithm on each individual image. Boundary conditions are introduced in order to keep a constant image size without distorting the estimated image boundaries. An algorithm is implemented in C in both the floating-point and fixed-point representations. The quantization error between the two representations is negligible. The RLdeconvolution algorithm is fully ported on an FPGA-based platform (i.e., Xilinx Zynq-7020) using the hardware description language VHDL. Two architectures are designed and called Architecture-1 and Architecture-2. The former is optimized with respect to the communication time with an external memory and the latter is optimized for limited storage. Both architectures are parameterized with respect to the image size and run-time configurable with respect to the number of iterations. In addition, Architecture-2 is run-time configurable with respect to the kernel size with a maximum kernel size equal to 9× 9. The execution time of implemented architectures is compared to a software only implementation of the algorithm running on the same Xilinx Zynq platform. A speed-up by a factor of 31 is achieved for Architecture-1 and a speed-up by a factor of 61 is achieved for Architecture-2. The execution time is also compared to a HW/SW implementation of the RL-deconvolution and a speed-up by a factor of 13 is achieved for Architecture-1 and a speed-up by a factor of 26 is achieved for Architecture-2. Compared to a state-of-the-art solution, a speed-up by a factor of 1.8 is achieved for the Architecture-2 when running a standard RL-deconvolution. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://ntnuopen.ntnu.no/ntnu-xmlui/bitstream/handle/11250/2624662/no.ntnu:inspera:39602101:18525947.pdf?isAllowed=y&sequence=1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
