Mitigation of cache memory using an embedded hard-core PPC440 processor in a Virtex-5 Field Programmable Gate Array.

Technical Report

Built-in self test for digital signal processor cores in virtex-4 and virtex-5 field programmable gate arrays (2010).

Thesis

Analysis and implementation of built-in self-test for block random access memories in virtex-5 field programmable gate arrays (2011).

Thesis

Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array

Article

An Embedded Flexible Content-Addressable Memory Core for Inclusion in a Field-Programmable Gate Array

Article

Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array.

Article

Soft core embedded processor based built-in self-test of FPGAs

Article

Ibm powerpc 405 seu mitigation using processor voting techniques in xilinx virtex-i1 pro fpga.

Article