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The Ksr1: Experimentation and Modeling of Poststore the Ksr1: Experimentation and Modeling of Poststore
| Content Provider | Semantic Scholar |
|---|---|
| Author | Apon, Amy W. Nashville, B. Vanderbilt University |
| Copyright Year | 1993 |
| Abstract | Kendall Square Research introduced the KSR1 system in 1991. The architecture is based on a ring of rings of 64-bit microprocessors. It is a distributed, shared memory system and is scalable. The memory structure is unique and is the key to understanding the system. Diierent levels of caching eliminates physical memory addressing and leads to the ALLCACHE T M scheme. Since requested data may be found in any of several caches, the initial access time is variable. However, once pulled into the local (sub)cache, subsequent access times are xed and minimal. Thus, the KSR1 is a Cache{Only Memory Architecture (COMA) system. This paper describes experimentation and an analytic model of the KSR1. The focus is on the poststore programmer option. With the poststore option, the programmer can elect to broadcast the updated value of a variable to all processors that might have a copy. This may save time for threads on other processors, but delays the broadcasting thread and places additional traac on the ring. The speciic issue addressed is to determine under what conditions poststore is beneecial. The analytic model and the experimental observations are in good agreement. They indicate that the decision to use poststore depends both on the application and the current system load. |
| File Format | PDF HTM / HTML |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
