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Test Synthesis from Register-Transfer Level Descriptions
| Content Provider | Semantic Scholar |
|---|---|
| Author | Raik, Jaan Paomets, Priidu |
| Copyright Year | 1996 |
| Abstract | Current paper presents a test synthesis system from register-transfer level (RTL) descriptions. The system includes test generators for datapath and control parts of the design and utilizes a logic-level synthesis tool. In the system, different design abstraction levels (RTL and gate-level) are described by alternative graph (AG) models. The uniform AG representation allows application of common formalism and procedures on these levels. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.pld.ttu.ee/~jaan/PDF/p009.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |