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A Static Single-Phase Clock D-Latch for UV-Programmable Floating-Gate MOSFET Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Linnarsson, Fredrik Aunet, Snorre Oelmann, Bengt |
| Copyright Year | 2003 |
| Abstract | In this work we present a static single-phase clock D-latch in floating-gate technique. The D-latch contains only six transistors, which makes it the most efficient one reported in literature. It is designed to operate in the subthreshold region. Its performance has been characterized by SPICE simulations for a 0.6 μm CMOS process and a power-supply voltage of 800 mV. Its maximum clocking frequency is 45 MHz and the power-delay product (PDP) is 28 fJ, which is at least two orders of magnitude lower than its counterparts operating in strong inversion. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://apachepersonal.miun.se/~benoel/download/papers/Dlatch.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
