Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors

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An optimum mapping of IPs for On-Chip Network design based on the minimum latency constraint

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Physical mapping and performance study of a multi-clock 3-dimensional network-on-chip mesh.

Tree-model based mapping for energy-efficient and low-latency Network-on-Chip

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Dynamic Application Mapping Algorithm for Wireless Network-on-Chip

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An analytical latency model for networks-on-chip.

3-d mesh-based optical network-on-chip for multiprocessor system-on-chip.

Power-aware mapping for network-on-chip architectures under bandwidth and latency constraints.

Unified multi-objective mapping for network-on-chip using genetic-based hyper-heuristic algorithms

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