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Parametric analysis and optimization of MOSFET macromodels for ESD circuit simulation
| Content Provider | Semantic Scholar |
|---|---|
| Author | Dettenborn, Robert Willian |
| Copyright Year | 2018 |
| Abstract | Electrostatic discharge (ESD) is a major reliability concern in semiconductor industry. An ESD event may degrade or destroy an integrated circuit (IC), impacting on production yields, manufacturing costs, product quality, product reliability and company profitability. Additionally, the breakdown voltages and failure currents of semiconductor devices are becoming lower with the technology scaling, placing severe constraints on robust IC design. As a result, effective onchip ESD protection without compromising area and performance requirements is becoming a challenge in deeply-scaled technologies. In this context, circuit simulation can provide the required assistance in on-chip protection design, including robustness analysis of the circuits and performance prediction prior to silicon. However, modeling the MOSFET operation under ESD conditions for circuit simulation is still a challenging issue. The large current and voltage characteristics are typically not well covered by most standard SPICE compact models. To overcome such limitation, a practical modeling approach is highly desired. This work presents a study of MOSFET macromodels for ESD circuit simulation. First, it gives an overview of the device operation under ESD conditions. Then, it presents the evolution of MOSFET macromodels for ESD circuit simulation. Finally, a novel macromodel development approach based on parametric analysis and optimization is introduced. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.lume.ufrgs.br/bitstream/handle/10183/193480/001089244.pdf?isAllowed=y&sequence=1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
