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Associative ternary cache for IP routing
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2001 |
| Abstract | A study of a prefix routing cache for Internet IP routing is presented. An output port assignment requires one cache memory access when the assignment is found in cache. The cache array is divided into sets that are of variable size; all entries within a set have the same prefix size. The cache is based on a ternary content addressable memory that matches ones, zeroes and don’t care values. Our study shows that an associative ternary cache provides an output port at the speed of one memory access with a very high hit rate. For an 8K entry cache the hit rate ranges from 97.62 to 99.67% on traces of 0.2 to 3.5 million addresses. A port error occurs when the port selected by the cache differs from the port that would have been selected from the routing table. A sampling technique is introduced that reduces the worst port error rate by an order of magnitude (from 0.52 to 0.05%). |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ece.ncsu.edu/asic/ece792A/2009/ECE792A/Readings_files/Routing6.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | 8K resolution Addresses (publication format) CPU cache Content-addressable memory Routing table Sampling (signal processing) Thrombocytopenia Tracing (software) |
| Content Type | Text |
| Resource Type | Article |
