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Power Efficient Design of 4 Bit Asynchronous Up Counter Using D Flip Flop
| Content Provider | Semantic Scholar |
|---|---|
| Author | Miranji, K. Suryanarayana, V. Kumar, N. S. |
| Copyright Year | 2014 |
| Abstract | D flip flops are the basic memory element which is used in many of the applications. Due to increase in demand of portable devices the research in low power has tremendously increased. In this we have discussed about the existing 18T latch and proposed a new 14T flip flop with that latch which has reduced area and power when compared to the existing ones. With this proposed and existing flip flop an asynchronous up/down counter was designed. Power comparison was made between the counters where the asynchronous counter designed using proposed flip flop gives low power consumption when compared to the existing one. Latch is an electronic device which is used to store one bit of data information. When the clock pin at positive edge the output of the D flip-flop takes the state of the D input and delays it by one clock cycle. Hence it is known as delay flip-flop. Latches are used as buffers but flip flops are used as a registers. Flip flop is the basic memory cell which is used to store the value on the data line. It has an advantage that the output is being synchronized by a lock. Many logic synthesis tools use only D latch and D flip flop. The power consumption and area are the main criterion"s considered while designing it. In today"s world power dissipation became a major thing. In today"s world power dissipation is the major problem as the high power dissipation leads to reduced time of operation, reduced mobility, high efforts of cooling, operational costs and reduced reliability. As the portable devices needs a good battery life time the low power consumption is needed. In digital systems counter circuits are used for many purposes. The number of occurrences of certain events is counted by using the counters and they generate timing intervals for control of various tasks in a system, keep track of time elapsed between specific events, Frequency synthesizers, frequency dividers and so on. Different types of counters are used in a variety of circuits. Here in this paper a 18 transistor D latch was discussed and from which a 14 transistor D flip flop is proposed and both the designs are compared and an asynchronous up/down counter was designed by using the existing and proposed D flip flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops and they do not have a global clock like synchronous counter. The proposed and conventional designs are simulated and analyzed in MICROWIND at 1 GHz (90 nm CMOS). |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.iject.org/vol5/spl3/ec1173.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
