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Pipelined High Speed Double Precision Floating Point Multiplier Using Dadda Algorithm Based on FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kumar, J. Rupesh Mohan, Gayathri Ram Sudershanraju |
| Copyright Year | 2015 |
| Abstract | Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented in HDL. This paper presents a high speed binary double precession floating point multiplier based on Dadda Algorithm. To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry Save Multiplier. In addition, the proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijera.com/special_issue/NCDATES/ECE/PART-5/ECE%20166-6064.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
