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A 12-bit 500-MSamples/s Current–Steering CMOS D/A Converter
| Content Provider | Semantic Scholar |
|---|---|
| Author | Tsai, S. T. Hung, A. Hung, Chung-Chih |
| Copyright Year | 2006 |
| Abstract | . Digital-To-Analog converters are essential components of modern applications, such as digital signal synthesis, video signal processing, and both wired and wireless transmitters. For data converters used in communications applications, the integral nonlinearity (INL) and differential nonlinearity (DNL) are not sufficient to characterize the performance. It is more convenient to characterize the performance in the frequency domain using measures as the spurious-free dynamic range (SFDR). The major target specification for SFDR of this paper, a 12-bit 500-MSample/s D/A converter, is 60 dB for signal frequencies up to 170 MHz. An additional design goal was to derive maximum benefit from this relatively advanced technology. This architecture is divided into a coarse sub-DAC and a binary-weighted fine sub-DAC. The differential switches of current sources are controlled by de glitch latch. The routing complexity and parasitic capacitance have to be considered for speed and signal synchronization. A 12-bit 500-MSample/s current-steering D/A converter integrated in a TSMC 0.18μm CMOS technology is presented. It is based on a current steering doubly segmented 8 + 4 architecture |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://ir.nctu.edu.tw/bitstream/11536/78426/1/361302.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
