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Banked Multiported Register File for Superscalar Microprocessors
| Content Provider | Semantic Scholar |
|---|---|
| Author | Tseng, Jessica H. Asanovic, Krste |
| Copyright Year | 2003 |
| Abstract | Introduction: Multiported register files and bypass networks lie at the heart of a superscalar microprocessor core, providing buffered communication of register values between producer and consumer instructions. As issue widths increase, both the number of ports and the number of registers required increase, causing the area of a conventional multiported register file to grow more than quadratically. Therefore, we examine the design of banked multiported register file that employ multiple interleaved banks of fewer ported register cells to reduce power and area. Banked register files designs have been shown to provide sufficient bandwidth for a superscalar machine, but these previous designs had complex control structures that would likely limit cycle time and add to design complexity. We develop a banked register file with much simpler and faster control logic while only slightly increasing the number of ports per bank. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://scale.eecs.berkeley.edu/papers/abstracts/regfile.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
