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VNS/LDS+CP : A Hybrid Method for Constraint Optimization in Anytime Contexts
| Content Provider | Semantic Scholar |
|---|---|
| Author | Loudni, Samir Boizumault, Patrice |
| Copyright Year | 2001 |
| Abstract | A digital signal processing circuit formed on a single integrated chip includes a multiplier for multiplying a multiplicand and multiplier signal to produce a multiple bit product signal having higher order bits delayed more than lower order bits; a first delay circuit for concatenating and delaying the multiplier and multiplicand signals to produce a delayed concatenated signal having higher order bits delayed more than lower order bits; a first selector for selectively supplying either the product signal, the delayed concatenated signal, or a concatenated signal formed from the multiplier and multiplicand signals, as a first selected signal; an adder for adding an input signal to the first selected signal to produce a summed signal; a second delay circuit for delaying a summed signal by a predetermined amount to produce a first delayed summand signal; a third delay circuit for delaying the summand signal to produce a second delayed summand signal having higher order bits delayed more than lower order bits; a second selector for selectively supplying either the first or second delayed summand signal to the adder as the input signal; a fourth delay circuit for delaying the summed signal by a predetermined amount to produce a first delayed summed signal; a fifth delay circuit for delaying the summed signal to produce a second delayed summed signal having lower order bits delayed more than higher order bits; and a third selector for selectively supplying either the first or second delayed summed signal as an output of the processing circuit. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://143.129.203.3/eume/MIC2001/MIC2001_761_766.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
