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Relaxing Persistent Memory Constraints with Hardware-Driven Undo + Redo Logging
| Content Provider | Semantic Scholar |
|---|---|
| Author | Ogleari, Matheus A. Miller, Ethan L. |
| Copyright Year | 2016 |
| Abstract | Persistent memory is a new tier of memory that functions as a hybrid of traditional storage systems and main memory. It combines the benefits of both: the data persistence property of storage with the fast load/store interface of memory. Yet, efficiently supporting data persistence in memory requires non-trivial effort. In particular, logging is a widely used data persistence scheme due to its portability and flexibility benefits compared with logless mechanisms. However, traditional software logging mechanisms are expensive to adopt in persistent memory, due to their overhead on performance, energy, and implementation. Additionally, alternate proposed hardware-based logging schemes don't fully address the issues with software. To address the challenges, we propose a hardware-driven undo+redo logging scheme, which maintains data persistence by leveraging the otherwise largely wasted hardware information available in the cache hierarchy. Our method allows persistent memory to exploit undo+redo logging to relax data persistence constraints on caching without nonvolatile on-chip buffering or caching components. Our evaluation across persistent memory microbenchmarks and real workloads demonstrates that our design leads to significant system throughput improvement and reduction in both dynamic energy and memory traffic. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://users.soe.ucsc.edu/~jzhao/files/HardwareLogging-techreport2016.pdf |
| Alternate Webpage(s) | https://users.soe.ucsc.edu/~jzhao/files/HardwareLogging.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
