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Instruction Scheduling and Executable Editing 1
| Content Provider | Semantic Scholar |
|---|---|
| Author | Schnarr, Eric Larus, James R. |
| Copyright Year | 1996 |
| Abstract | Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and actual performance, while frustrating for computer architects and chip manufacturers, opens the exciting possibility of low-cost or even no-cost instrumentation for measurement, simulation, or emulation. Instrumentation code that executes in previously unused processor cycles is effectively hidden. These microprocessors also pose another problem, which arises from the machine-specific instruction scheduling necessary for high performance. Different implementations of an architecture, such as the many x86 processors, may benefit from different schedules, which either requires multiple executables or a way to reschedule existing programs for new machines. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ftp.cs.wisc.edu/wwt/wcsss96_eel.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
