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Highly linear 2.5-V CMOS /spl Sigma//spl Delta/ modulator for ADSL+
| Content Provider | Semantic Scholar |
|---|---|
| Author | Río, Rocío Del Rosa, J. M. De La Pérez-Verdú, Belén Delgado-Restituto, Manuel Domínguez-Castro, Rafael Medeiro, Fernando Rodríguez-Vázquez, Ángel |
| Copyright Year | 2004 |
| Abstract | We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator. |
| Starting Page | 47 |
| Ending Page | 62 |
| Page Count | 16 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/TCSI.2003.821308 |
| Volume Number | 51 |
| Alternate Webpage(s) | https://www.researchgate.net/profile/Manuel_Delgado-Restituto/publication/3450671_Highly_linear_2.5-V_CMOS__modulator_for_ADSL/links/02bfe513732aececcc000000.pdf |
| Alternate Webpage(s) | http://digital.csic.es/bitstream/10261/3730/1/High%20linear.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/TCSI.2003.821308 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
