Circuit for Generating a Datastrobe Signal Used in a Double Data Rate Synchronous Semconductor Device Background of the Invention

Content Provider	Semantic Scholar
Copyright Year	2017
Abstract	Provided is a circuit for generating a data Strobe Signal used in a double data rate (DDR) synchronous semiconductor device. The circuit comprises a first logic unit capable of generating a pull up control Signal responsive to first and Second clock Signals. A Second logic unit is capable of generating a pull down signal responsive to the first and Second clock Signals. A data Strobe buffer is capable of generating a data Strobe Signal responsive to the pull up and pull down control Signals, the data Strobe Signal including a preamble. The first logic unit is capable of generating the preamble responsive to a first pulse of the first clock signal. And the data Strobe Signal is in a high impedance State responsive to a last pulse of the first clock signal.
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Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article