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Microarchitectural Simulator for Shader Cores in a Modern GPU Simulation Infrastructure
| Content Provider | Semantic Scholar |
|---|---|
| Author | González, Antonio |
| Copyright Year | 2019 |
| Abstract | Mobile devices have emerged as one of the most rapidly spread technologies, with users spending a significant amount of time playing games on these devices. The evolution of smartphone games along with a supplementary increase in resolution has lead to a growing demand for more visually compelling graphics on mobile devices, which require significant energy consumption to maintain. However, the battery capacity of these devices does not grow at the same time as the computing capabilities, creating an everincreasing gap. Therefore, it has become increasingly important to facilitate the study of energy-efficient architectures for GPUs in mobile devices. Inspite of this, accurate full-system simulators for mobile graphics systems are rare. TEAPOT is a cycle-accurate simulator for mobile-GPU systems and is the state of the art in this area. There were certain aspects of the shader core in TEAPOT that were identified to be capable for improvement. The objective of this project is to redesign the shader cores in TEAPOT to match the contemporary microarchitecture of shader cores. The register file was changed and a banking mechanism used. A new stage named ‘Operand Collector’ was added in order to buffer instructions with register bank conflicts. A new Issue Scheduling mechanism was implemented. The width of the pipeline was changed to two. An I-Buffer was included in the Fetch stage. The Execute unit was pipelined and more write ports were added to the Writeback stage. After this, the functionality and accuracy of the new features of the implemented model were validated using various tests. The tests involved observing different metrics of the shader core, like IPC, while some parameters of the newly implemented model were varied. Lastly, three experiments were conducted in order to explore some microarchitectural designs with a representative set of current mobile graphics applications. With these, we first studied the improvement in performance using the register allocation scheme used in TEAPOT. We also found the optimum range of the total number of warps and the optimum register file size for the benchmarks used. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://upcommons.upc.edu/bitstream/handle/2117/170041/144359.pdf?isAllowed=y&sequence=1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
