Electroless Deposition On Self-Assembled Monolayers As a Method to Enable Fabrication of Advanced Interconnects

Content Provider	Semantic Scholar
Author	Caro, Aranzazu Maestre Chebiam, Ramanan V. Teugels, L. Clendenning, Scott B. Clarke, James S.
Copyright Year	2013
Abstract	Density scaling of integrated circuits for future electronic devices presents some manufacturing challenges. For Example, the classic thin film deposition techniques used in the fabrication of the back-end-of-line interconnects, such as PVD (Physical vapor deposition), are not extendable for wires sizes below 20nm [1]. Robust sidewall coverage from a line of sight PVD process is difficult to achieve at small dimensions as there is a risk of feature pinch off blocking the subsequent plating and filling of the wires. This will lead to voiding and poor line resistance and reliability. On the other hand, depending on EP to fill features with thin seed could lead to sidewall voiding due to seed dissolution in the bath and large terminal effects across the wafer. The problems faced by a PVD/EP process for gap fill will be further magnified if the wafer size is increased from 300mm to 450mm. Furthermore, below the 20nm feature size, the performance of the barrier/seed/electro-plating approach is no longer acceptable. The volume taken by the barrier dramatically reduces the conductor volume .Therefore the resistivity increases exponentially with scaling. For that reason, new approaches need to be used in order to facilitate the aggressive dimensions of new technology nodes. Possible ways to tackle these limitations are the use of platable SAMs (self-assembled monolayers) as a path for new conformal metallization techniques such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition) or EL (Electroless deposition) in order to extend copper diffusion barriers and to search for alternative metals to copper based on material properties like diffusivity into ILDs and metal resistivity [2, 3]. In this work we present Ni electroless deposition on SAMs as alternative barrier candidate against copper diffusion and an alternative to PVD/EP-fill approach for small dimensions interconnects. A catalyzed SAM layer acts as a seed for Ni electroless plating. The layer conformably grows from the sidewalls until a specific barrier thickness is achieved as shown in Figure 1 and Cu EL grows directly on the metallic barrier filling the feature with no seam. As a result of the EL implementation sub-20nm lines are filled with either Cu or Ni EL with no voiding present as shown in Figure 2 a), b) and c).
Starting Page	2368
Ending Page	2368
Page Count	1
File Format	PDF HTM / HTML
DOI	10.1149/ma2013-02/38/2368
Alternate Webpage(s)	https://ecs.confex.com/ecs/224/webprogram/Abstract/Paper23158/F5-2368.pdf
Alternate Webpage(s)	https://doi.org/10.1149/ma2013-02%2F38%2F2368
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article