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Area-Delay-Power analysis of Carry Look-AheadAdder Architecture
| Content Provider | Scilit |
|---|---|
| Author | Prasad, Ch. Rajendra Srikanth, Y. Rao, P. Ramchandar Kumar, S. Sanjay |
| Copyright Year | 2020 |
| Description | Journal: Iop Conference Series: Materials Science and Engineering The addition is common in hardware for the microprocessor and digital signal processor (DSP), and an adder is used to execute the addition. The Adder should feature high speed and low power for real-time applications. An effective adder architecture principally advances the performance of microprocessors and DSP systems. The carry propagation delay (CPD) is the main apprehension in the design of adder architecture. To address CPD, a new Carry Look-Ahead architecture is proposed, in which the carry propagation is scheduled before the calculation of the final sum using carry look–ahead (CLA) method. A quantitative estimate shows that the Area Delay Product (ADP) of proposed adder architecture is minimized by 10% as compared with the existing adders’ architectures. |
| Related Links | https://iopscience.iop.org/article/10.1088/1757-899X/981/3/032022/pdf |
| ISSN | 17578981 |
| e-ISSN | 1757899X |
| DOI | 10.1088/1757-899x/981/3/032022 |
| Journal | Iop Conference Series: Materials Science and Engineering |
| Issue Number | 3 |
| Volume Number | 981 |
| Language | English |
| Publisher | IOP Publishing |
| Publisher Date | 2020-12-01 |
| Access Restriction | Open |
| Subject Keyword | Journal: Iop Conference Series: Materials Science and Engineering Hardware and Architecture |
| Content Type | Text |
| Resource Type | Article |
