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Energy-Efficient ADC Topology Enabled with Asynchronous Techniques
| Content Provider | Scilit |
|---|---|
| Author | Chen, Shuo-Wei Mike |
| Copyright Year | 2018 |
| Description | The proposed asynchronous analog-to-digital converter (ADC) with nonbinary successive approximation topology provides a path heading toward high power efficiency, sampling speed, and bandwidth without the need of a higher-than-sampling-rate clock. Before the booming of complementary metal oxide semiconductor (CMOS) technology, Silicon Germanium (SiGe) and gallium arsenide (GaAs) were a popular choice for making high-speed ADCs, which could be often seen in many radar systems and instruments. In this chapter, the authors aim to explore the cost limit of CMOS ADC for going toward higher speed and bandwidth by using ADC architecture. For low conversion speeds, a successive approximation converter (SAR) approach is often used since it also divides a full conversion into several comparison stages in a way similar to the pipeline ADC, except the algorithm is executed sequentially rather than in parallel as in the pipeline case. Instead of a binary successive approximation scheme, the ADC adopts redundancy to allow dynamic decision errors for faster conversion speed. Book Name: Circuits at the Nanoscale |
| Related Links | https://content.taylorfrancis.com/books/download?dac=C2009-0-06295-X&isbn=9781315218762&doi=10.1201/9781315218762-14&format=pdf |
| Ending Page | 243 |
| Page Count | 19 |
| Starting Page | 225 |
| DOI | 10.1201/9781315218762-14 |
| Language | English |
| Publisher | Informa UK Limited |
| Publisher Date | 2018-10-08 |
| Access Restriction | Open |
| Subject Keyword | Book Name: Circuits at the Nanoscale Hardware and Architecturee Asynchronous Successive Approximation |
| Content Type | Text |
| Resource Type | Chapter |
