NDLI: CMOS Focal Plane Spatially Oversampling Computational Image Sensor

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CMOS Focal Plane Spatially Oversampling Computational Image Sensor

Content Provider	Scilit
Author	Olyaei, Ashkan Genov, Roman
Copyright Year	2018
Description	Many video processing applications employ spatial image transforms such as block-matrix and convolutional transforms. This chapter presents a mixed-signal very large-scale integration (VLSI) implementation of a digital complementary metal oxide semiconductor (CMOS) imager computing block-matrix and convolutional transforms on the focal plane for real-time image processing. The computational image sensor combines image acquisition, signal processing, and quantization in a single compact low-power architecture. The approach combines weighted spatial averaging and oversampling quantization in a single algorithmic sigma–delta-modulated analog-to-digital converter (ADC) cycle, making focal-plane computing an intrinsic part of the quantization process. The approach yields power dissipation below that of a conventional digital imager while the need for a peripheral digital signal processor (DSP) is eliminated. The chapter compares the presented architecture with a conventional approach where column-parallel algorithmic ADCs performing no computation are employed and an additional peripheral serial digital multiplier and accumulator performs video compression. Book Name: Circuits at the Nanoscale
Related Links	https://content.taylorfrancis.com/books/download?dac=C2009-0-06295-X&isbn=9781315218762&doi=10.1201/9781315218762-26&format=pdf
Ending Page	502
Page Count	18
Starting Page	485
DOI	10.1201/9781315218762-26
Language	English
Publisher	Informa UK Limited
Publisher Date	2018-10-08
Access Restriction	Open
Subject Keyword	Book Name: Circuits At the Nanoscale Hardware and Architecturee Quantization Computing Digital Employ Focal Plane Presented Computational Image
Content Type	Text
Resource Type	Chapter

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