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Instruction Precomputation conductor Inc.; 2University of Rhode Island; 3University of Minnesota at
| Content Provider | Scilit |
|---|---|
| Copyright Year | 2005 |
| Description | As a program executes, some computations are performed over and over again. These redundant computations increase the program's execution time since they could require multiple cycles to execute and because they consume limited processor resources. To minimize the performance degradation that redundant computations have on the processor, instruction precomputation hardware can be used to dynamically remove these redundant computations. Instruction precomputation profiles the program to determine the highest frequency redundant computations. These computations then are loaded into the Precomputation Table before the program executes. During program execution, the processor accesses the Precomputation Table to determine whether or not an instruction is a redundant computation; instructions that are redundant receive their output value from the Precomputation Table and are removed from the pipeline. The key difference between instruction precomputation and value reuse – another microarchitectural technique that dynamically removes redundant computations – is that instruction precomputationdoes not dynamically update the Precomputation Table with the most recent redundant computations since it already contains those that occur with the highest frequency. For a 2048-entry Precomputation Table, dynamically removing redundant computations yields an average speedup of 10.53%, while, by comparison, a 2048-entry Value Reuse Table produces an average speedup of 7.43%. Book Name: Speculative Execution in High Performance Computer Architectures |
| Related Links | https://api.taylorfrancis.com/content/chapters/edit/download?identifierName=doi&identifierValue=10.1201/9781420035155-17&type=chapterpdf |
| Ending Page | 284 |
| Page Count | 24 |
| Starting Page | 261 |
| DOI | 10.1201/9781420035155-17 |
| Language | English |
| Publisher | Informa UK Limited |
| Publisher Date | 2005-05-26 |
| Access Restriction | Open |
| Subject Keyword | Book Name: Speculative Execution in High Performance Computer Architectures Hardware and Architecturee Speedup Reuse Execution Instruction Precomputation Removed Table Redundant Computations |
| Content Type | Text |
| Resource Type | Chapter |
