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A method of synthesis of irredundant circuits admitting single fault detection tests of constant length
| Content Provider | Scilit |
|---|---|
| Author | Romanov, Dmitry S. Romanova, Elena Yu. |
| Copyright Year | 2019 |
| Abstract | A constructive proof is given that in each of the bases B′ = {x&y, x⊕y, x ∼ y}, B1 = {x&y, x⊕y, 1} any n-place Boolean function may be implemented: by an irredundant combinational circuit with n inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates) a single fault detection test of length at most 16, by an irredundant combinational circuit with n inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most 2n−2log2 n+O(1); besides, there exists an n-place function that cannot be implemented by an irredundant circuit admitting a detecting test whose length is smaller than 2n−2log2 n − Ω(1), by an irredundant combinational circuit with n inputs and three outputs admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most 17. |
| Related Links | http://www.degruyter.com/downloadpdf/j/dma.2019.29.issue-1/dma-2019-0005/dma-2019-0005.xml |
| Ending Page | 48 |
| Page Count | 14 |
| Starting Page | 35 |
| ISSN | 09249265 |
| e-ISSN | 15693929 |
| DOI | 10.1515/dma-2019-0005 |
| Journal | Discrete Mathematics and Applications |
| Issue Number | 1 |
| Volume Number | 29 |
| Language | English |
| Publisher | Walter de Gruyter GmbH |
| Publisher Date | 2019-02-25 |
| Access Restriction | Open |
| Subject Keyword | Discrete Mathematics and Applications Hardware and Architecturee Circuit of Gates Fault Detection Test Stuck-at Fault Shannon Function Easily Testable Circuit Journal: Discrete Mathematics and Applications, Vol- 29, Issue- 1 |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Discrete Mathematics and Combinatorics |
