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Asynchronous on-chip networks
| Content Provider | Scilit |
|---|---|
| Author | Amde, Manish Felicijan, Tomaz Efthymiou, Aristides Edwards, Douglas Lavagno, Luciano |
| Copyright Year | 2006 |
| Description | The main idea of an SoC design methodology is to 'divide' complex chips into several independent functional blocks and 'conquer' each of them using standard synchronous methodologies and existing CAD tools. These functional blocks are then connected by the means of an on-chip communication infrastructure to form a functional system. In this chapter we first present formal frameworks for the analysis of transformations from synchronous to asynchronous systems, and their implementation in the desynchronisation flow. Next we discuss speed-independent circuits and their logic synthesis techniques. We then proceed to explain various schemes for implementing GALS-based systems. We finally conclude with a discussion on asynchronous NoCs, and with a case study. |
| Related Links | http://apt.cs.manchester.ac.uk/ftp/pub/apt/papers/aris_IEE05.pdf |
| Ending Page | 656 |
| Page Count | 32 |
| Starting Page | 625 |
| DOI | 10.1049/pbcs018e_ch18 |
| Language | English |
| Publisher | Institution of Engineering and Technology (IET) |
| Publisher Date | 2006-01-01 |
| Access Restriction | Open |
| Subject Keyword | Book Name: System-on-Chip: Next Generation Electronics Hardware and Architecture Asynchronous Noc Cad Tools Soc Design Methodology Asynchronous On-chip Networks Desynchronisation Flow Speed-independent Circuits On-chip Communication Infrastructure Logic Synthesis Techniques Gals-based Systems |
| Content Type | Text |
| Resource Type | Article |
