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QCA Implementation of Reversible and Non-reversible Ripple Carry Adder
| Content Provider | NIT Kurukshetra |
|---|---|
| Advisor | Sasamal, Trailokya Nath |
| Researcher | Kumawat, Rohit |
| Date Awarded | 2016-01-01 |
| Abstract | Limitations of present complementary metal oxide semiconductor (CMOS) technology are heat dissipation, power dissipation, scaling problem and performance degradation. These problems can be resolved by adopting new emerging technologies like quantum-dot cellular automata (QCA) and reversible logic technology, which provides a new horizon in low power computation. Reversible logic technology handles heat dissipation problem very effectively whereas remaining problems can be easily taken care by QCA. Using reversible logic technology, inputs can be retrieved from outputs and vice-versa. QCADesigner tool 2.0.3 has been used for designing of any logical expression using reversible and non-reversible logic gates. QCADesigner 2.0.3 tool is used to match the simulation results for all the designs. The proposed adder's performance is enhanced by proper placement of the inverters and 3-input majority gate in the layout. Reversible full adder and 4-bit ripple carry adder (RCA) are implemented using Peres gate (PG) in QCADesigner tool. The proposed Peres gate requires 137 cells which cover an area of 0.13nm2 with one clock cycle delay. The proposed reversible full adder is evaluated and achieves 60%, 19.7% and 50% improvement in the area, complexity (no. of cells) and delay respectively. Similarly proposed reversible 4-bit RCA gains 73.8%, 29.3% and 28.6% significant improvement in area, complexity and delay respectively. The designs of non-reversible 1-bit, 4-bit and 8-bit adders are improved with respect to presently existing QCA designs. By using multilayer crossover technique, the complexity and area have been reduced with the same latency. |
| Page Count | 56 |
| File Format | |
| Language | English |
| Publisher Department | Department of Electronics & Communication Engineering |
| Publisher Institution | National Institute of Technology, Kurukshetra |
| Publisher Place | Kurukshetra, Haryana |
| Access Restriction | Open |
| Subject Keyword | Comparison of Nonreversible Adders Comparison of Reversible Adders Feynman Gate Fredkin Gate Full Adder in QCA Gates of QCA Nonreversible Design of Bit, Bit and Bit Rca NOT Gate Peres Gate in QCA QCA Based Designs of Nonreversible Adders QCA Based Designs of Reversible Adders QCA Cell QCA Clock QCA Crossover QCA Implementation of Reversible and Nonreversible Ripple Carry Adder QCA Wire Reversible Bit Rca in QCA Reversible Design of Bit and Bit Adders Reversible Logic Gates Reversible ML Adder in QCA Simulation Results of Nonreversible Bit RCA Simulation Results of Nonreversible Full Adder Simulation Results of Peres Gate Simulation Results of Reversible Bit Rca Simulation Results of Reversible Full Adder Toffoli Gate |
| Content Type | Text |
| Educational Degree | Master of Technology (M.Tech.) |
| Resource Type | Thesis |