A Study of Design and Analysis of Energy Efficient Full Adder

Content Provider	NIT Kurukshetra
Advisor	Santosh, Sandeep
Researcher	Panjeta, Ashwani Kumar
Date Awarded	2013-07-01
Abstract	The main objective of this thesis is to design and analyse different types of adders and compare them with hybrid full adder in ISOrnn standard CMOS process. Various adders like conventional CMOS full adder, lOT Ml adder, 14T full adder, transmission gate ftill adder were simulated and compared with hybrid adder. Finally comparison of all the full adders based on static CMOS logic and pass transistor logic was done ,their power dissipation , delay, power delay product were calculated and it was observed that hybrid adder performance was best.In hybrid adder since it uses both the logics so it will provide lesser power dissipation and lesser power delay product. The hybrid adder with all other adders was designed and simulated using mentor graphics tool in ISOnm technology. The frequency used is 200MHz. For all the full adders voltage supply of 1.8V was taken, and it was observed from simulation results that hybrid adder perform better than all other adders and have minimum power delay products.
Page Count	66
File Format	PDF
Language	English
Publisher Department	Department of Electronics & Communication Engineering
Publisher Institution	National Institute of Technology, Kurukshetra
Publisher Place	Kurukshetra, Haryana
Access Restriction	Open
Subject Keyword	CMOS Logic Famiues Complementary Pass Transistor Logic Conventional Static Logic Data Driven Dynamic Circuit Design Architect Design of Hybrid Full Adder Domino Logic Dynamic Circuit Dynamic Logic Circuit Fourteen Transistor (T) Full Adder Keeper Low Count Transistor Full Adder Module XR/XNR Output Waveforms Pass Transistor Based Full Adder Schematic of Different Full Adder Q Six Transistor Based Xor Gate Ten Transistor Full Adder Transmission Gate Full Adder
Content Type	Text
Educational Degree	Master of Technology (M.Tech.)
Resource Type	Thesis