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Feasibility Prediction for Rapid IC Design Space Exploration
| Content Provider | MDPI |
|---|---|
| Author | Islam, Riadul |
| Copyright Year | 2022 |
| Description | The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This research applied a machine learning approach to automatically identify design constraints and design rule checking (DRC) violation issues and help the designer identify design constraints with optimal DRCs before the long detailed routing process through iterative greedy search. The proposed algorithm achieved up to 99.99% design constraint prediction accuracy and reduced 98.4% DRC violations with only a 6.9% area penalty. |
| Starting Page | 1161 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics11071161 |
| Journal | Electronics |
| Issue Number | 7 |
| Volume Number | 11 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2022-04-06 |
| Access Restriction | Open |
| Subject Keyword | Electronics Information and Library Science Design Rule Check Electronic Design Automation (eda) Decision Tree Ic Design Design Constraints |
| Content Type | Text |
| Resource Type | Article |
