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Compact Hardware Architectures of Enocoro-128v2 Stream Cipher for Constrained Embedded Devices
| Content Provider | MDPI |
|---|---|
| Author | Pyrgas, Lampros |
| Copyright Year | 2020 |
| Description | Lightweight cryptography is a vital and fast growing field in today’s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz clock and reaches a throughput equal to 302 Mbps, while at the same time, it utilizes only 254 Look-up Tables (LUTs) and 330 Flip-flops (FFs). Each round of computations requires 5 clock cycles. The 4-bit implementation has an operating frequency of 204 MHz and reaches a throughput equal to 181 Mbps, with each round requiring 9 clock cycles. The 4-bit implementation utilizes 249 LUTs and 343 FFs. To our knowledge, this is the first time that such implementations of the Enocoro-128v2 are presented. Both implementations utilize a very low number of resources (only 78 FPGA slices are required for the 8-bit architecture and only 83 for the 4-bit one) and the results demonstrate that they are sustainable for area constrained embedded devices. |
| Starting Page | 1505 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics9091505 |
| Journal | Electronics |
| Issue Number | 9 |
| Volume Number | 9 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2020-09-14 |
| Access Restriction | Open |
| Subject Keyword | Electronics Hardware and Architecturee Enocoro-128v2 Stream Cipher Fpga Implementations Lightweight Cryptography Hardware Security Constrained Embedded Devices |
| Content Type | Text |
| Resource Type | Article |
