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A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
| Content Provider | MDPI |
|---|---|
| Author | Tang, Zixiang Lv, Fangxu Shi, Jianjun Zhang, Jinwang Wei, Jiahang Wang, Xinjie |
| Copyright Year | 2022 |
| Description | To reduce the high bit error rate of serial transceivers under strong channel attenuation, a low-power 112 Gb/s SerDes transmitter was designed using a duo-binary PAM4 modulation technology. By adopting duo-binary PAM4 modulation technology, the problem of the low bandwidth utilization of a high-speed PAM4 (pulse amplitude modulation 4) signal was improved. The problem of high jitter caused by charge sharing and the limited bandwidth of a 4:1 high-speed MUX was improved by using precharging auxiliary transistors. The system power consumption of the transmitter was reduced by using a 7-bit weighted voltage-driven digital-to-analog converter (DAC). The transmitter was designed with a 28 nm CMOS process and powered by a voltage of 0.9 V. The simulation results showed that when the channel attenuation was 20.9 dB, the transmitter could work at 112 Gb/s, the power consumption was 2.02 pJ/bit, and the linearity was 96.7%. |
| Starting Page | 2486 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics11162486 |
| Journal | Electronics |
| Issue Number | 16 |
| Volume Number | 11 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2022-08-10 |
| Access Restriction | Open |
| Subject Keyword | Electronics Strong Channel Duo-binary Pam4 Modulation Transmitter Charge in Advance Digital-to-analog Converter (dac) |
| Content Type | Text |
| Resource Type | Article |
