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Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios
| Content Provider | MDPI |
|---|---|
| Author | Dadaliaris, Antonios Kranas, George Oikonomou, Panagiotis Floros, George Dossis, Michael |
| Copyright Year | 2022 |
| Description | Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its result, paired with the outcome of the routing procedure can be the decisive factor in rendering a design manufacturable. Global placement generates an optimized instance of the design targeting a set of metrics, while ignoring rules pertaining its feasibility. Legalization and detailed placement rectify this situation, attempting to attain minimum quality loss by often disregarding the connectivity between cells and making runtime the focal point of these steps. In this article, we present a set of variations on a connectivity-based legalization scheme that can either be applied as a legalizer or a detailed placer. The variations can be applied in the entirety of the chip area or in the confinement of a user-specified bin while they are guided by various optimization goals, e.g., total wire length, displacement and density. We analytically describe our variations and evaluate them through extensive simulations on commonly used benchmarks. |
| Starting Page | 212 |
| e-ISSN | 20782489 |
| DOI | 10.3390/info13050212 |
| Journal | Information |
| Issue Number | 5 |
| Volume Number | 13 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2022-04-20 |
| Access Restriction | Open |
| Subject Keyword | Information Standard Cell Placement Legalization Detailed Placement Standard Cell Design |
| Content Type | Text |
| Resource Type | Article |
