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A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA
| Content Provider | MDPI |
|---|---|
| Author | Ángel Rodríguez-Vázquez, Ricardo, Carmona-Galán Parsakordasiabi, Mojtaba Vornicu, Ion |
| Copyright Year | 2021 |
| Description | In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources. |
| Starting Page | 308 |
| e-ISSN | 14248220 |
| DOI | 10.3390/s21010308 |
| Journal | Sensors |
| Issue Number | 1 |
| Volume Number | 21 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2021-01-05 |
| Access Restriction | Open |
| Subject Keyword | Sensors Nuclear Energy and Engineering Field Programmable Gate Array (fpga) Tapped-delay-line (tdl) Thermometer-to-binary (t2b) Encoder Multichannel Tdcs Time-to-digital Converter (tdc) Time-of-flight (tof) Single-photon Avalanche Diode (spad) |
| Content Type | Text |
| Resource Type | Article |
