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Synapse-Neuron-Aware Training Scheme of Defect-Tolerant Neural Networks with Defective Memristor Crossbars
| Content Provider | MDPI |
|---|---|
| Author | An, Jiyong Oh, Seok Jin Nguyen, Tien Van Min, Kyeong-Sik |
| Copyright Year | 2022 |
| Description | To overcome the limitations of CMOS digital systems, emerging computing circuits such as memristor crossbars have been investigated as potential candidates for significantly increasing the speed and energy efficiency of next-generation computing systems, which are required for implementing future AI hardware. Unfortunately, manufacturing yield still remains a serious challenge in adopting memristor-based computing systems due to the limitations of immature fabrication technology. To compensate for malfunction of neural networks caused from the fabrication-related defects, a new crossbar training scheme combining the synapse-aware with the neuron-aware together is proposed in this paper, for optimizing the defect map size and the neural network’s performance simultaneously. In the proposed scheme, the memristor crossbar’s columns are divided into 3 groups, which are the severely-defective, moderately-defective, and normal columns, respectively. Here, each group is trained according to the trade-off relationship between the neural network’s performance and the hardware overhead of defect-tolerant training. As a result of this group-based training method combining the neuron-aware with the synapse-aware, in this paper, the new scheme can be successful in improving the network’s performance better than both the synapse-aware and the neuron-aware while minimizing its hardware burden. For example, when testing the defect percentage = 10% with MNIST dataset, the proposed scheme outperforms the synapse-aware and the neuron-aware by 3.8% and 3.4% for the number of crossbar’s columns trained for synapse defects = 10 and 138 among 310, respectively, while maintaining the smaller memory size than the synapse-aware. When the trained columns = 138, the normalized memory size of the synapse-neuron-aware scheme can be smaller by 3.1% than the synapse-aware. |
| Starting Page | 273 |
| e-ISSN | 2072666X |
| DOI | 10.3390/mi13020273 |
| Journal | Micromachines |
| Issue Number | 2 |
| Volume Number | 13 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2022-02-08 |
| Access Restriction | Open |
| Subject Keyword | Micromachines Industrial Engineering Synapse-neuron-aware Training Defect-tolerant Neural Networks Defective Memristor Crossbars Memristor Defects Neuromorphic |
| Content Type | Text |
| Resource Type | Article |
