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An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors
| Content Provider | MDPI |
|---|---|
| Author | Romero-Zaliz, Rocio Cantudo, Antonio Perez, Eduardo Jimenez-Molinos, Francisco Wenger, Christian Roldan, Juan Bautista |
| Copyright Year | 2021 |
| Description | We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on |
| Starting Page | 3141 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics10243141 |
| Journal | Electronics |
| Issue Number | 24 |
| Volume Number | 10 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2021-12-17 |
| Access Restriction | Open |
| Subject Keyword | Electronics Hardware and Architecturee Memristor Multilevel Operation Hardware Neural Network Deep Neural Network Convolutional Neural Network Network Architecture Synaptic Weight |
| Content Type | Text |
| Resource Type | Article |