NDLI: Discrete-level memristive circuits for HTM-based spatiotemporal data classification system

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Discrete-level memristive circuits for HTM-based spatiotemporal data classification system

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Discrete-level memristive circuits for HTM-based spatiotemporal data classification system

Content Provider	IET Digital Library
Author	Irmanova, Aidana Ibrayev, Timur James, Alex Pappachen
Abstract	The authors propose a discrete-level memristive memory design for analogue data processing in hardware implementations of hierarchical temporal memory (HTM). In this study, memristors were set to ternary and quaternary states in a sub-cell by application of different write voltage levels through a resistive network configuration. Simulations of the proposed circuit show that the highest number of discrete output levels of the memory was achieved using quaternary logic. However overall, using the same number of sub-cells and ternary logic exhibits the lowest relative error rate. For data classification purposes, the proposed discrete-level memristive cells are incorporated into the TM of HTM architecture, and its hardware circuit is presented for pattern recognition. They report improved results of face recognition using AR, ORL and UFI databases, and TIMIT database for speech recognition. These results are compared with the earlier design of HTM having only the spatial pooler (SP). Accuracy of the HTM architecture incorporating both SP and TM with discrete-level memristive cells for face recognition increased from 76.5 to 83.5% for AR database and speech recognition accuracy is improved from 73.3 to 93.3%.
Starting Page	34
Ending Page	43
Page Count	10
Volume Number	3
e-ISSN	23983396
Issue Number	Issue 1, Mar (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cps/3/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cps.2017.0053
Journal	IET Cyber-Physical Systems: Theory & Applications
Publisher	The Institution of Engineering and Technology
Publisher Date	2017-10-01
Access Restriction	Open
Rights License	Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Subject Keyword	Analogue Data Processing Data Handling Technique Discrete-level Memristive Cell Discrete-level Memristive Circuit Discrete-level Memristive Memory Design Face Recognition Hardware Circuit Hardware Implementations Hierarchical Temporal Memory HTM Architecture HTM-based Spatiotemporal Data Classification System Memory Architecture Memory Circuit Memristor Circuit Memristors Pattern Classification Pattern Recognition Quaternary Logic Quaternary State Resistive Network Configuration Resistor Spatial Pooler Speech Recognition Storage Requirements Write Voltage Levels
Content Type	Text
Resource Type	Article

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