NDLI: Efficient implementation of iterative multi-input–multi-output orthogonal frequency-division multiplexing receiver using minimum-mean-square error interference cancellation

Content Provider	IET Digital Library
Author	Han, Bing Yang, Zengli Zheng, Yahong Rosa
Abstract	An efficient hardware implementation scheme is proposed for iterative multi-input–multi-output orthogonal frequency-division multiplexing receiver which includes an MMSE-IC (minimum-mean-square error interference cancellation) detector, a channel estimator, a low-density parity-check (LDPC) decoder and other supporting modules. The proposed implementation uses the QR decomposition (QRD) of the complex-valued matrices with four coordinate rotation digital computer (CORDIC) cores and a back substitution to solve the MMSE-IC equations while the existing systolic array architectures require 15–38 CORDIC cores to achieve a similar throughput. The proposed 4-CORDIC QRD architecture can be configured as a 16-matrix or a 64-matrix pipelining by using a different number of multipliers combined with one-dimensional (1D) or 2D arrays of the back substitution, respectively. The channel estimator implements a commonly-used frequency domain least squares channel estimation with the canonic-signed-digits method, thanks to the character of the Zadroff-Chu sequence used as the pilot. In the LDPC decoder, the min-sum algorithm is implemented for the quasicyclic LDPC decoding. The two schemes for the MMSE-IC detector with different throughput and resource usages have been implemented in a Field Programmable Gate Array for a complete baseband turbo receiver. Their resource usages, throughputs and latencies are compared with the classic systolic array architectures, which demonstrate that the proposed receiver architecture achieves the best tradeoff between the throughput and the resource usage.
Starting Page	990
Ending Page	999
Page Count	10
ISSN	17518628
Volume Number	8
e-ISSN	17518636
Issue Number	Issue 7, May (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-com/8/7
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-com.2013.0694
Journal	IET Communications
Publisher Date	2014-02-21
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	1D Arrays 2D Arrays 4-CORDIC QRD Architecture Baseband Turbo Receiver Canonic-signed-digit Method Channel Estimation Classic Systolic Array Architectures Code Communication Channel Equalisation And Identification Complex-valued Matrices Coordinate Rotation Digital Computer Cores CORDIC Cores Cyclic Codes Decoding Digital Arithmetic Method Electromagnetic Compatibility Field Programmable Gate Array Frequency Domain Analysis Frequency Domain Least Square Channel Estimation Hardware Implementation Scheme Interference Interference Suppression Interpolation And Function Approximation Iterative Method Iterative Multiple-input Multiple-output Orthogonal Frequency-division Multiplexing Receiver LDPC Decoder Least Mean Squares Method Logic Circuit Low-density Parity-check Decoder MIMO Communication Min-sum Algorithm Minimum Mean Square Error Interference Cancellation MMSE-IC Detector MMSE-IC Equation Numerical Analysis OFDM Modulation One-dimensional Array Parity Check Code QR Decomposition Quasicyclic LDPC Decoding Radio Frequency Interference Radio Link And Equipment Receiver Architecture Resource Usages Systolic Array Zadroff-Chu Sequence Character
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Science Applications

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