NDLI: Joint detection–decoding of majority-logic decodable non-binary low-density parity-check coded modulation systems: an iterative noise reduction algorithm

Content Provider	IET Digital Library
Author	Zhao, Shancheng Wang, Xuepeng Wang, Teng Bai, Baoming Ma, Xiao
Abstract	In this study, the authors present a low-complexity iterative joint detection–decoding algorithm for majority-logic decodable non-binary low-density parity-check (LDPC) coded modulation systems. In the proposed algorithm, a hard-in–hard-out decoder is combined with a hard-decision signal detector in an iterative manner. Each iteration consists of five phases. Firstly, the detector makes hard decisions based on the iteratively updated ‘received’ signals; secondly, these hard decisions are distributed via variable nodes to check nodes; thirdly, check nodes compute hard extrinsic messages; fourthly, each variable node counts hard extrinsic messages from its adjacent check nodes and feeds back to the detection node the symbol with the most votes as well as the difference between the most votes and the second most votes; finally, these feedbacks are used to shift each ‘received’ signal point along an estimated direction to possibly reduce noise. The proposed algorithm requires only integer operations and finite field operations and consequently can be implemented with simple combinational logic circuits in practical systems. Simulation results show that the proposed algorithm performs well and hence serves as an attractive candidate for trading off performance against complexity for majority-logic decodable non-binary LDPC codes.
Starting Page	1810
Ending Page	1819
Page Count	10
ISSN	17518628
Volume Number	8
e-ISSN	17518636
Issue Number	Issue 10, Jul (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-com/8/10
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-com.2013.0684
Journal	IET Communications
Publisher Date	2014-05-19
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Adjacent Check Nodes Code Combinational Circuit Combinational Logic Circuit Flnite Fleld Operation Hard Extrinsic Message Computation Hard-decision Signal Detector Hard-in-hard-out Decoder Integer Operation Interpolation And Function Approximation Iterative Decoding Iterative Noise Reduction Algorithm Iteratively Updated Received Signal LDPC Logic Circuit Low-complexity Iterative Joint Detection-decoding Algorithm Majority-logic Decodable Low-density Parity-check Coded Modulation System Modulation Coding Nonbinary Low-density Parity-check Coded Modulation System Numerical Analysis Parity Check Code Signal Denoising Signal Detection Variable Node
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Science Applications

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