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| Content Provider | IET Digital Library |
|---|---|
| Author | Li, Bingchao Wei, Jizeng Guo, Wei Sun, Jizhou |
| Abstract | GPGPUs adopt SIMT execution model inwhich each logical thread in a warp corresponds to a SIMDlane while can still follow an independent control flow.When a branch divergence appears and threads within awarp take different execution paths, GPGPUs have to execute each path serially through SIMD lane masking, whichpotentially decreases the SIMD utilization and performance. We propose an efficient thread compaction mechanism to handle branch divergence with a novel register filestructure. We also develop a new thread scheduling policycooperating with our compaction mechanism. The simulation results show that our approach improves the SIMDutilization up to 74.4% and achieves a maximum 11.1%performance speedup with small hardware overhead. |
| Starting Page | 684 |
| Ending Page | 688 |
| Page Count | 5 |
| ISSN | 10224653 |
| Volume Number | 24 |
| e-ISSN | 20755597 |
| Issue Number | Issue 4, Oct (2015) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/cje/24/4 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/cje.2015.10.004 |
| Journal | Chinese Journal of Electronics |
| Publisher Date | 2015-10-01 |
| Access Restriction | Open |
| Rights Holder | © Chinese Institute of Electronics |
| Subject Keyword | Branch Divergence GPGPU Graphics Processing Units Microprocessor Chips Multiprocessing System Parallel Processing Register File Structure SIMD Utilization Thread Compaction Mechanism Thread Scheduling Policy Thread-lane Shuffled Compaction |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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