NDLI: A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator

Content Provider	IET Digital Library
Author	Zhao, Yuyue Jiang, Yingdan Yang, Yu Shen, Guangzhen Hu, Kai Yan, Hua
Abstract	The proposed Clock and data recovery system (CDRS) has three improved parts. The second order digital filter with rounding algorithm implements fractional gain and avoids direct current quantization noise which varies between -q/2 and +q/2 while that of traditional filter varies between 0 and +q (q is quantization step). The hysteresis majority voter can combat high frequency and strong jitter especially in quasi-steady state. The improved Phase interpolator (PI) has much smaller current-switching glitch and phase glitch since the weighting current changes gradually instead of steeply. The optimized CDRS can handle up to ±6000ppm (parts per million) frequency offset and the phase resolution is 1.4º/LSB (Least significant bit) according to analysis. The simulations of jitter transfer function and jitter tolerance by Matlab, simulations of phase noise by spectre using Verilog+VeriloA model, and measurements of frequency offset and jitter tolerance all show its good performance.
Starting Page	1227
Ending Page	1233
Page Count	7
ISSN	10224653
Volume Number	28
e-ISSN	20755597
Issue Number	Issue 6, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/cje/28/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/cje.2019.08.006
Journal	Chinese Journal of Electronics
Publisher Date	2019-11-01
Access Restriction	Open
Rights Holder	© Chinese Institute of Electronics
Subject Keyword	A/D And D/A Convertor CDR System Clock And Data Recovery Circuit Current-switching Glitch Data Recovery System Digital Filter Direct Current Quantization Noise General Circuit Analysis And Synthesis Method Hysteresis Majority Voter Jitter Jitter Transfer Function Phase Interpolator Phase Noise Phase Resolution Quantisation (signal) Quantization Step Second Order Digital Filter Transfer Function
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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