NDLI: Reduced carrier PWM scheme with unified logical expressions for reduced switch count multilevel inverters

Content Provider	IET Digital Library
Author	Vemuganti, Hari Priya Sreenivasarao, Dharmavarapu Kumar, Ganjikunta Siva Spandana, Appikonda Sai
Abstract	The significant reduction in switch count of symmetrical/asymmetrical reduced switch count multilevel inverters (RSC-MLI) topologies has modified the operation of inverter such that the conventional carrier-based pulse width modulation (PWM) schemes such as level-shifted PWM and phase-shifted PWM can no more realise them. To control these RSC-MLI topologies, reduced carrier PWM schemes with modified switching logic gained more prominence. These schemes involve suitable logical expressions to realise the switching states of the inverter. However, these logical expressions vary with topological arrangement and number of levels. Moreover, these schemes produce high total harmonic distortion (THD) in line-voltages. Therefore, to improve the line-voltage THD and generalise the switching logic, a modified reduced carrier PWM scheme with unified logical expressions is presented here. The proposed PWM scheme is directly valid for any topology and can be easily scalable to any number of levels in the inverters. To validate the implementation of the proposed PWM to control any RSC-MLI, experimental studies of various asymmetrical RSC-MLI topologies with the proposed PWM scheme are carried out. Further, to verify the superiority of the proposed scheme in terms of THD, complexity, scalability, and computation burden, its performance is compared with carrier-based PWM schemes reported in the literature.
Starting Page	912
Ending Page	921
Page Count	10
ISSN	17554535
Volume Number	11
e-ISSN	17554543
Issue Number	Issue 5, May (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-pel/11/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-pel.2017.0586
Journal	IET Power Electronics
Publisher Date	2018-01-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Asymmetrical RSC-MLI Topology Circuit Configuration Harmonic Distortion Inverter Switching State Line-voltage THD Logic Circuit Logical Expressions Modified Reduced Carrier PWM Scheme Modified Switching Logic Network Topology Power Electronics Power Supply PWM Invertors Reduced Switch Count Multilevel Inverter Topology Supervisory Circuit Topological Arrangement Total Harmonic Distortion Unified Logical Expressions
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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