NDLI: FPGA-assisted state-of-polarisation generation for polarisation-encoded optical communications

Content Provider	IET Digital Library
Author	Muga, Nelson J. Ramos, Mariana F. Mantey, Sara T. Silva, Nuno A. Pinto, Armando N.
Abstract	This study presents a theoretical model for polarisation manipulation using electronic polarisation controllers (EPCs) based on fibre squeezing. A method to calculate the EPC configuration in order to transform between two arbitrary states of polarisation (SOP) is presented. After, a technique to deterministically generate four SOPs for use in polarisation-encoded quantum communication systems is proposed. Moreover, the effectiveness of the proposed technique is experimentally assessed through the generation of two pairs of orthogonal SOPs. The experimental implementation used an field programmable gate array (FPGA) board to electrically control the four waveplates of the EPC, reaching a rate of 500 qubit/s. Results show that this polarisation generation process is intrinsically stable, demonstrating its potential for practical implementations of polarisation-encoding quantum key distribution systems using the BB84 and B92 protocols.
Starting Page	350
Ending Page	355
Page Count	6
ISSN	17518768
Volume Number	14
e-ISSN	17518776
Issue Number	Issue 6, Dec (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-opt/14/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-opt.2020.0035
Journal	IET Optoelectronics
Publisher Date	2020-06-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Arbitrary States Electronic Polarization Controller Encoding EPC Configuration Fibre Squeezing Field Programmable Gate Array Field Programmable Gate Array Board FPGA-assisted State-of-Polarisation Generation Light Polarisation Logic Circuit Optical Communication Orthogonal SOPs Polarisation Generation Process Polarisation Manipulation Polarisation-encoded Optical Communication Polarisation-encoded Quantum Communication System Polarisation-encoding Quantum Key Distribution System Protocol Quantum Communication Quantum Computation Quantum Cryptography Quantum Optics SOP
Content Type	Text
Resource Type	Article
Subject	Atomic and Molecular Physics, and Optics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

A Real-Time QKD System Based on FPGA

FPGA Based ASM implementation for CCD Camera Controller

Optimised field programmable gate array implementation of a dual-mode orthogonal frequency division multiplexing optical wireless communication transmitter

A Compact Single-FPGA Fading-Channel Simulator

Floating Gate-Based Field Programmable Mixed-Signal Array

Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation

High-Performance Pulsed-Power Generator Controlled by FPGA

FPGA-assisted state-of-polarisation generation for polarisation-encoded optical communications

Similar Documents

Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

A Real-Time QKD System Based on FPGA

FPGA Based ASM implementation for CCD Camera Controller

Optimised field programmable gate array implementation of a dual-mode orthogonal frequency division multiplexing optical wireless communication transmitter

A Compact Single-FPGA Fading-Channel Simulator

Floating Gate-Based Field Programmable Mixed-Signal Array

Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation

High-Performance Pulsed-Power Generator Controlled by FPGA

FPGA-assisted state-of-polarisation generation for polarisation-encoded optical communications