NDLI: Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement

Content Provider	IET Digital Library
Author	Li, Shih An Tsai, Chi Yi
Abstract	This study presents a cost-efficient and high-performance field programmable gate array (FPGA)-based hardware implementation of a contrast-preserving image dynamic range compression algorithm, which is an important function used in modern digital video cameras and displays to improve visual quality of standard dynamic range colour images (8 bits/channel). To achieve this purpose, a hardware-friendly approximation to an existing fast dynamic range compression with local contrast preservation (FDRCLCP) algorithm is proposed. The computation of the proposed approximated FDRCLCP algorithm requires only fixed-point unsigned binary addition, multiplication, and bit-shifting. Moreover, the proposed hardware implementation uses a line buffer instead of a frame buffer to process whole image data. These advantages significantly improve throughput performance and reduce memory requirement of the system. The FPGA implementation of the proposed algorithm requires only about 98 K bits on-chip memory and achieves about 170.24 MHz operating frequency by using an Altera Cyclone II device. This is a large improvement compared with the existing results as it is quick enough to process full high-definition videos (1920 × 1080 pixels) at least 80 frames per second using a low-cost FPGA device.
Starting Page	605
Ending Page	614
Page Count	10
ISSN	17519659
Volume Number	9
e-ISSN	17519667
Issue Number	Issue 8, Aug (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-ipr/9/8
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-ipr.2014.0162
Journal	IET Image Processing
Publisher Date	2015-08-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Altera Cyclone II Device Approximation Theory Computer Vision And Image Processing Technique Contrast-preserving Image Dynamic Range Compression Algorithm Data Compression Digital Video Camera Fast Dynamic Range Compression with Local Contrast Preservation Algorithm FDRCLCP Algorithm Field Programmable Gate Array Fixed-point Unsigned Binary Addition FPGA Full-HD Video Enhancement Hardware-friendly Approximation Image And Video Coding Image Colour Analysis Image Enhancement Interpolation And Function Approximation Logic And Switching Circuit Logic Circuit Numerical Analysis Video Coding Video Signal Processing Visual Quality
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering Computer Vision and Pattern Recognition Software

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